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| PD- 95081A IRLR024NPBF IRLU024NPbF HEXFET(R) Power MOSFET l l l l l l l Logic-Level Gate Drive Surface Mount (IRLR024N) Straight Lead (IRLU024N) Advanced Process Technology Fast Switching Fully Avalanche Rated Lead-Free D VDSS = 55V RDS(on) = 0.065 G S ID = 17A Description Fifth Generation HEXFET(R) Power MOSFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible onresistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. The D-PAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount applications. D-Pak I-Pak IRLR024NPBF IRLU024NPbF Absolute Maximum Ratings Parameter ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Max. 17 12 72 45 0.3 16 68 11 4.5 5.0 -55 to + 175 300 (1.6mm from case ) Units A W W/C V mJ A mJ V/ns C Thermal Resistance Parameter RJC RJA RJA Junction-to-Case Case-to-Ambient (PCB mount)** Junction-to-Ambient Typ. --- --- --- Max. 3.3 50 110 Units C/W www.irf.com ** When mounted on 1" square PCB (FR-4 or G-10 Material ) . For recommended footprint and soldering techniques refer to application note #AN-994 1 12/6/04 IRLR/U024NPbF Electrical Characteristics @ TJ = 25C (unless otherwise specified) V(BR)DSS V(BR)DSS/TJ Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance RDS(on) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LD LS Ciss Coss Crss Min. Typ. Max. Units Conditions 55 --- --- V VGS = 0V, ID = 250A --- 0.061 --- V/C Reference to 25C, I D = 1mA --- --- 0.065 VGS = 10V, ID = 10A --- --- 0.080 VGS = 5.0V, ID = 10A --- --- 0.110 VGS = 4.0V, ID = 9.0A 1.0 --- 2.0 V VDS = VGS, ID = 250A 8.3 --- --- S VDS = 25V, ID = 11A --- --- 25 VDS = 55V, VGS = 0V A --- --- 250 VDS = 44V, VGS = 0V, TJ = 150C --- --- 100 VGS = 16V nA --- --- -100 VGS = -16V --- --- 15 ID = 11A --- --- 3.7 nC VDS = 44V --- --- 8.5 VGS = 5.0V, See Fig. 6 and 13 --- 7.1 --- VDD = 28V --- 74 --- ID = 11A ns --- 20 --- RG = 12, VGS = 5.0V --- 29 --- RD = 2.4, See Fig. 10 Between lead, 4.5 nH 6mm (0.25in.) G from package --- 7.5 --- and center of die contact --- 480 --- VGS = 0V --- 130 --- pF VDS = 25V --- 61 --- = 1.0MHz, See Fig. 5 D S Source-Drain Ratings and Characteristics IS ISM VSD trr Qrr ton Notes: Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time Min. Typ. Max. Units Conditions D MOSFET symbol --- --- 17 showing the A G integral reverse --- --- 72 S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 11A, VGS = 0V --- 60 90 ns TJ = 25C, IF = 11A --- 130 200 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11) Pulse width 300s; duty cycle 2%. This is applied for I-PAK, LS of D-PAK is measured between lead and center of die contact VDD = 25V, starting TJ = 25C, L = 790H RG = 25, IAS = 11A. (See Figure 12) TJ 175C ISD 11A, di/dt 290A/s, VDD V(BR)DSS, Uses IRLZ24N data and test conditions. 2 www.irf.com IRLR/U024NPbF 100 VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP 100 10 ID , Drain-to-Source Current (A) ID , Drain-to-Source Current (A) VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP 10 2.5V 1 1 2.5V 20s PULSE WIDTH TJ = 25C 0.1 1 10 0.1 100 A 0.1 0.1 20s PULSE WIDTH T J = 175C 1 10 100 A VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 100 3.0 TJ = 25C R DS(on) , Drain-to-Source On Resistance (Normalized) I D = 17 A 18A I D , Drain-to-Source Current (A) 2.5 TJ = 175C 10 2.0 1.5 1 1.0 0.5 0.1 2 3 4 5 6 V DS = 15V 20s PULSE WIDTH 7 8 9 10 A 0.0 -60 -40 -20 0 20 40 60 VGS = 10V 80 100 120 140 160 180 A VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature (C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3 IRLR/U024NPbF 800 VGS , Gate-to-Source Voltage (V) C, Capacitance (pF) 600 Ciss V GS = 0V, f = 1MHz C iss = Cgs + C gd , Cds SHORTED C rss = C gd C oss = C ds + C gd 15 I D = 11A V DS = 44V V DS = 28V 12 9 400 Coss 6 200 Crss 3 0 1 10 100 A 0 0 4 8 FOR TEST CIRCUIT SEE FIGURE 13 12 16 20 A VDS , Drain-to-Source Voltage (V) Q G , Total Gate Charge (nC) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 100 1000 ISD , Reverse Drain Current (A) OPERATION IN THIS AREA LIMITED BY R DS(on) I D , Drain Current (A) TJ = 175C TJ = 25C 10 100 10s 10 100s 1 0.4 0.8 1.2 1.6 VGS = 0V A 1 1 TC = 25C TJ = 175C Single Pulse 10 1ms 10ms 2.0 100 A VSD , Source-to-Drain Voltage (V) VDS , Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRLR/U024NPbF 20 V DS VGS RD ID , Drain Current (A) 15 RG 5V D.U.T. + -VDD 10 Pulse Width 1 s Duty Factor 0.1 % Fig 10a. Switching Time Test Circuit 5 VDS 90% 0 25 50 75 100 125 150 175 TC , Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature 10% VGS td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms 10 Thermal Response (Z thJC ) D = 0.50 1 0.20 0.10 0.05 0.1 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = t P DM t 1 t2 1 /t 2 0.01 0.00001 2. Peak TJ = PDM x Z thJC + T C A 1 0.0001 0.001 0.01 0.1 t 1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRLR/U024NPbF E AS , Single Pulse Avalanche Energy (mJ) 140 TOP 120 15V BOTTOM ID 4.5A 7.8A 11A 100 VDS L DRIVER 80 RG 20V D.U.T IAS tp + V - DD 60 A 0.01 40 Fig 12a. Unclamped Inductive Test Circuit 20 0 VDD = 25V 25 50 75 100 125 150 A 175 V(BR)DSS tp Starting TJ , Junction Temperature (C) Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50K QG 12V .2F .3F 10 V QGS QGD VGS 3mA D.U.T. + V - DS VG Charge IG ID Current Sampling Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit 6 www.irf.com IRLR/U024NPbF Peak Diode Recovery dv/dt Test Circuit D.U.T + + Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer - + RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test + VDD Driver Gate Drive P.W. Period D= P.W. Period VGS=10V * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt VDD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% ISD * VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFET(R) MOSFETs www.irf.com 7 IRLR/U024NPbF D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) D-Pak (TO-252AA) Part Marking Information EXAMPLE: T HIS IS AN IRFR120 WIT H ASS EMBLY LOT CODE 1234 ASS EMBLED ON WW 16, 1999 IN T HE AS S EMBLY LINE "A" Note: "P" in as sembly line pos ition indicates "Lead-Free" INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER IRFU120 12 916A 34 DAT E CODE YEAR 9 = 1999 WEEK 16 LINE A OR INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER IRFU120 12 34 DAT E CODE P = DES IGNATES LEAD-FREE PRODUCT (OPT IONAL) YEAR 9 = 1999 WEEK 16 A = AS S EMBLY S IT E CODE 8 www.irf.com IRLR/U024NPbF I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) I-Pak (TO-251AA) Part Marking Information EXAMPLE: T HIS IS AN IRFU120 WIT H AS S EMBLY LOT CODE 5678 AS S EMBLED ON WW 19, 1999 IN T HE AS S EMBLY LINE "A" Note: "P" in assembly line position indicates "Lead-Free" INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER IRF U120 919A 56 78 DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A OR INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER IRFU120 56 78 DAT E CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPTIONAL) YEAR 9 = 1999 WEEK 19 A = AS S EMBLY S IT E CODE www.irf.com 9 IRLR/U024NPbF D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR TRL 16.3 ( .641 ) 15.7 ( .619 ) 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. Data and specifications subject to change without notice. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.12/04 10 www.irf.com |
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